1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to a method of counting event occurrences in a computer system for performance monitoring.
2. Description of the Related Art
As electronic systems become more complicated, there is a greater need for monitoring the performance of the systems to ensure optimum operation and identify any defects or design problems. This concern is particularly important for integrated circuits such as processors used in computer systems. An exemplary processor 10 is illustrated in FIG. 1, and includes various execution units, registers, buffers, memories, and other functional units which are all formed by integrated circuitry. Processor 10 is coupled to a system or fabric bus 12 via a bus interface unit (BIU) 14 within processor 10 which controls the transfer of information between processor 10 and other devices coupled to system bus 12, such as a main memory. BIU 14 is connected to an instruction cache and memory management unit (MMU) 16, and to a data cache and MMU 18. High-speed caches, such as those within instruction cache and MMU 16 and data cache and MMU 18, enable processor 40 to achieve relatively fast access time to a subset of data or instructions previously transferred from main memory to the caches, thus improving the speed of operation of the host data processing system. Instruction cache and MMU 16 is further coupled to a sequential fetcher 20, which fetches instructions for execution from instruction cache and MMU 16 during each cycle. Sequential fetcher 20 transmits branch instructions fetched from instruction cache and MMU 16 to a branch prediction unit 22 for calculating the next instruction fetch address, but temporarily stores sequential instructions within an instruction queue 24 for execution by other execution circuitry within processor 10. The execution circuitry of processor 10 has multiple execution units for executing sequential instructions, including one or more fixed-point units (FXUs) 26, load-store units (LSUs) 28, floating-point units (FPUs) 30, and branch processing units (BPUs) 32. These execution units 26, 28, 30, and 32 execute one or more instructions of a particular type during each processor cycle, utilizing source operands received from specified general purpose registers (GPRs) 34 or GPR rename buffers 36, or from floating-point registers (FPRs) 38 or FPR rename buffers 40.
Today's processors typically provide performance monitoring counters that count the time, cycles, or other types of events between a first event and a second event. For example, if latency is to be measured, the counted events are typically cycles, and typical start and stop events might be instruction fetch and instruction completion, load fetch and load completion, or cache miss and cache reload. Alternatively, if the reason for a large cache reload latency is being investigated, typical start and stop events might be cache load and cache reload, and the counted events might be load retries in the fabric, or some action that is performed in order to reload the cache.
In addition to counting events between a start and a stop event, it is often desirable to see if the number of counted events exceeds a given threshold, or to measure how frequently the number of counted events exceeds the threshold. In order to provide this additional functionality, the hardware can support a threshold register which contains the value against which the total number of counted events is to be compared.